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AT86RF232
11.6 Dynamic Frame Buffer Protection
11.6.1 Overview
The Atmel AT86RF232 continues the reception of incoming frames as long as it is in
any receive state. When a frame was successfully received and stored into the Frame
Buffer, the following frame will overwrite the Frame Buffer content again.
To relax the timing requirements for a Frame Buffer read access the Dynamic Frame
Buffer Protection prevents that a new valid frame passes to the Frame Buffer until a
Frame Buffer read access has ended (indicated by /SEL = H, refer to Section 6.2 ).
A received frame is automatically protected against overwriting:
? in Basic Operating Mode, if its FCS is valid
? in Extended Operating Mode, if an IRQ_3 (TRX_END) is generated
The Dynamic Frame Buffer Protection is enabled with RX_SAFE_MODE set and
applicable transceiver states RX_ON and RX_AACK_ON.
Note:
1.
The Dynamic Frame Buffer Protection only prevents write accesses from the air
interface – not from the SPI interface.
11.6.2 Register Description
Register 0x0C (TRX_CTRL_2):
The TRX_CTRL_2 register is a multi-purpose control register to control various settings
of the radio transceiver.
Figure 11-17 . Register TRX_CTRL_2.
Bit
0x0C
Read/Write
Reset value
Bit
0x0C
Read/Write
Reset value
7
RX_SAFE_MODE
R/W
0
3
R
0
6
R
0
2
R/W
0
reserved
5
reserved
R/W
1
1
R/W
0
4
R
0
0
R/W
0
TRX_CTRL_2
TRX_CTRL_2
? Bit 7 - RX_SAFE_MODE
Protect Frame Buffer after frame receive with valid FCF check.
Table 11-17. RX_SAFE_MODE.
Register Bits
RX_SAFE_MODE
Value
0
Description
Disable Dynamic Frame Buffer protection
1
(1)
Enable Dynamic Frame Buffer protection
Note:
1.
Dynamic Frame Buffer Protection is released with the rising edge of /SEL pin of a
Frame Buffer read access, or radio transceiver state changes from RX_ON or
RX_AACK_ON to another state.
This operation mode is independent of the setting of register bits RX_PDT_LEVEL,
(register 0x15, RX_SYN), refer to Section 9.1.3 .
143
8321A – MCU Wireless – 10/11
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